1. Field of Invention
The present invention relates to fabrication of a semiconductor device. More particularly, the present invention relates to a method of forming a shallow trench isolation structure (STI).
2. Description of Related Art
As semiconductor device integration continuously increases, device dimensions are necessarily accordingly reduced. An integrated circuit (IC) is composed of many devices and isolation structures that isolate the devices. The isolation structures, such as shallow trench isolation structures or field oxide isolation structures, are used to prevent carriers from moving between devices. Conventionally, the isolation structures are formed within a concentrated semiconductor circuit, for example, between adjacent field effect transistors (FET) in a dynamic random access memory (DRAM), to reduce a leakage current produced by the FET.
An isolation region is formed in an integrated circuit for preventing a short circuit from occurring between adjacent device regions on a substrate. Conventionally, a local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions on the semiconductor device. However, since internal stress is generated and bird's beak encroachment occurs in the isolation structures, LOCOS cannot effectively isolate devices.
The shallow trench isolation technique has been developed to improve the bird's beak encroachment of LOCOS so as to achieve an effective isolation structure. The conventional STI process is the sequential formation of a pad oxide layer and a silicon nitride layer on a substrate. A photolithography step is then performed to define STI areas. The silicon nitride layer, the pad oxide layer and the substrate are sequentially etched to form trenches in the substrate. Regions surrounded by STI are active areas (AA).
A liner oxide layer is formed on the surface of the trenches by thermal oxidation. A silicon dioxide layer is deposited in the trenches and above the silicon nitride mask layer by chemical vapor deposition (CVD). A chemical mechanical polishing (CMP) process is performed to remove the silicon dioxide layer that is higher than the silicon nitride layer to form a STI structure. Finally, hot phosphoric acid is used to remove the silicon nitride layer, and HF solution is used to remove the pad oxide layer.
Since the shallow trench isolation structure has a good isolation effect and its size is scaleable, it is often employed as a device isolation structure. The shallow trench isolation structure is the preferred isolation technique, especially for the fabrication of sub-half micron semiconductor devices.
FIG. 1 is a cross-sectional view schematically illustrating a conventional shallow trench isolation structure. As shown in FIG. 1, because the liner silicon dioxide layer 110 and the shallow trench isolation structure 120 are both made of silicon dioxide, a portion of the liner silicon dioxide layer 110 and a portion of the shallow trench isolation structure 120 are etched during the pad oxide layer etching process. A divot 130 is easily formed near the top corner of the shallow trench isolation structure 120 due to stress at the top corner of the shallow trench isolation structure 120. A depth of the divot 130 is about 800-1000 .ANG.. The divot 130 leads to a kink effect that causes a threshold voltage reduction. Moreover, in the subsequent poly gate process, polysilicon may fills the divot 130, so that a leakage current is generated. Therefore, the process window of the subsequent poly gate process should be narrowed to avoid the leakage current.
A pullback process is used to avoid the formation of the divot in the shallow trench isolation structure. The pullback process is described as follows. A portion of the silicon nitride layer is etched by, for example, wet etching with hot phosphoric acid to widen the opening in the silicon nitride layer. Therefore, the subsequently formed silicon dioxide layer not only fills the trench but also covers the pad oxide layer. When the pad oxide layer is removed with HF solution, no divot is formed in the shallow trench isolation structure even a portion of the shallow trench isolation structure is etched. In this manner, the leakage current is avoided.